Abstract

Most of the 65536 16-bit patterns form valid machine code instructions for the DDP-516 computer, About 1000 of the remainder are investigated in this report and it is shown that combinations of functions can be assembled usefully into a single instruction. As an example of this the Algol "sign" function is coded more economically than is possible in DAP. Some comments on the hardware are included, particularly on the "skip on zero accumulator" instruction and a list of the variants of instructions concludes the report.

Contents

1. Introduction
1.1 The Order Code of the DDP-516
2. The Skip Instructions
2.1 The Meaning of the Bits
2.2 Useful Microcoding
3. The Shift Instructions
4. The Generic Type B Instructions
5. The Generic Type A Instruction Set
5.1 The DAP Instructions
5.2 The Instruction Scan
5.3 Some Useful Microcoding
5.4 Character handling Microcodes
5.5 The ALGOL "sign" function
6. Comments on the hardware
6.1 The Skip Instructions
6.2 The Group B Generic Instructions
6.3 The Group A Generic Instructions
7. Summary of Generic Instructions, Group A

1. Introduction

Most small computers have a fixed instruction length, typically one word of from 12 to 18 bits, The DDP-516 computer under discussion in this report has a 16-bit word length and stores one instruction per word. Most of the 65536 bit patterns possible in a 16-bit word have a defined effect when used as instructions, but about 3250 patterns are not accounted for in the manuals. Since the PDP-8, 9 and 15 permit "micro coding" by combination of instructions, it was of interest to see if a similar technique was possible on the Honeywell DDP-516.

1.1 The Order Code of the DDP-516

The 16 instruction bits may be thought of as being divided up into 3 fields, a 2-bit flag field (F), a 4-bit op-code field (O) and a 10-bit address field (A).

FF0000AAAAAAAAAA

Where the op-code field takes on any of the values 101 to '13, '15 to '17 (using the apostrophe to signify an octal number), the instruction is a memory referencing one, and all possible combinations of FF and A....A are meaningful.

Likewise if the op-code is '14 a peripheral instruction is intended and all of these are, in principle,, defined.

If however the op-code is zero . the setting of the flag bits determines the type of the instruction as follows:

FF  
0 Generic instruction Type B
1 Shift instruction
2 Skip instruction
3 Generic instruction Type A.

The type A generic instruction is the most interesting but the others will be dealt with first.

2. The Skip Instructions

The general format of a skip instruction is (in binary)

1,0,0,0,0,0,R,P,M,E,Z,S1,S2,S3,S4,C

i.e. the first six bits are 100000 while the others describe the conditions under which the skip takes place.

2.1 The meaning of the bits

Leaving aside bit R, the other bits cause a skip if the following conditions are true.

P accumulator positive
M memory parity error
E accumulator even
Z accumulator zero
S1 sense switch 1 reset
S2 sense switch 2 reset
S3 sense switch 3 reset
S4 sense switch 4 reset
C C-bit zero.

The R bit, if set, reverses the skip decision. A few examples will make this clear.

SKP unconditional skip is '100000
NOP no skip is '101000
SRC skip if C reset is '100001
SSC skip if C set is '101001

2.2 Useful Micro coding

The instructions SSS (skip if any sense key set) and SSR (skip if all sense keys reset) are examples of microcoding included in the DAP repertoire. Their codes are '101036 and '100036 respectively. However any combination of the sense key bits may be used. E.g. '100030 will skip only if both sense keys 1 and 2 are reset, whereas '101030 will skip if either switch 1 or 2 is set.

This principle may be extended further, e.g. '100500 will skip only on positive even numbers while '101500 will skip on odd or negative numbers, '100041 will skip if both A and C are zero and '101041 will skip if either is non zero.

It is not possible to construct an instruction to skip if A > 0 or if A <= 0 due to the (rather careless) design of the logic, which is discussed in section 6.1.

3. The Shift Instructions

The format of the shift instructions is as follows:

0,1,0,0,0,0,C,C,C,C,L,L,L,L,L,L

where the code CCCC may take one of 12 values and the length of shift LLLLLL may range from 0 to 63.

The twelve types of legal shift are

CCCC    
'X0 LRL,LLL long logical shift
'X1 LRS,LLS long arithmetic shift
'X2 LRR,LLR long rotate
'X4 LGR,LGL logical shift
'X5 ARS,ALS arithmetic shift
'X6 ARR,ALR rotate

where X = 0 for right and I for left, The remaining codes, '03, '13, '07 and '17, give a curious combination of arithmetic and cyclic shifts. In a left shift the bits shifted off the top, reappear at the bottom and C is set by overflow. In the long shifts the A and B registers are given a 31 bit cyclic shift and B1 is unaffected. In the case of the right shifts the bits disappearing off the bottom end are logically "or-ed" into the top end, with propagation of the sign bit. Again B1 does not take part in the long shifts.

It is not envisaged that these shifts will be useful.

4. The Generic Type B Instructions

These instructions have the general form

000000CCCCCCCCC1

except for the HLT instruction which has the last bit zero. The instructions do not form a tidy group, but their effects are as follows:

'5 SGL Enter Single Precision Mode
'7 DBL Enter Double Precision Mode
'11 DXA Disable Extended Mode
'13 EXA Enter Extended Mode
'21 RMP Reset Memory Parity Error
'41 SCA Shift count to A
'43 INK Input Keys
'101 NRM Normalize
'201 IAB Interchange A and B
'401 ENB Enable Program Interrupt
'1001 INH Inhibit Program Interrupt
'1401 ERM Enter Restricted Mode

Combinations are not likely to be useful, but the SCA instruction transfers the contents of the E-register (bits 11 - 16) to the A register. This same register is used as a transfer in the IAB instruction so that '241 transfers the A to B registers and 6 bits to the A register.

However this instruction does not work unless the High Speed Arithmetic option is fitted.

5. The Generic type A Instruction Set

The type A generic instructions have the general form

110000XCCCCCCCCC

where X .... C contain the bits specifying action to be taken on the A-register and C-bit. The seventh bit X has no effect on the operation of any instruction although it is often set in the "official" instructions of the DAP-16 set.

5.1 The DAP Instructions

The operations listed in the Programmers' Manual are as follows:

'140024 CHS complement A1
'140040 CRA clear A
'140100 SSP set sign plus
'140200 RCB reset C bit
'140320 CSA copy sign and set plus
'140401 CMA complement A
'140407 TCA two's complement A
'140500 SSM set sign minus
'140600 SCB set C bit
'141044 CAR clear A right half
'141050 CAL clear A left half
'141140 ICL interchange and clear left
'141206 AOA add one to A
'141216 ACA add C to A
'141240 ICR interchange and clear right
'141340 ICA interchange A

To follow the operation of these instructions it is necessary to consider 3 of the 4 timing periods of the machine cycle, T2, T3 and T4. T1 and T2 are concerned with a standard setting up procedure such as fetching the instruction and moving on the P register by one.

The overlap between T2 and T3, known as TLATE may cause a one to be added into A if bit 15 is one and bit 13 is zero. (This will be written as (-13 & 15) in future). The ACA operation also may take place. Otherwise this period is spent in loading A into the adder. During T3, if bits 8 & 15 are both one then another half cycle (consisting of a repeat of T2 and T3) is called for. Normally this is only required for the TCA instruction, but other uses can be found for it, if (-9 & -11) then the D register is set to the complement of the A register during T3 otherwise it is set to A. via the adder.

Most of the action takes place during T4 when various parts of the D register are put back into the A register and C-bit, The actions are as follows:

bit(s)  
10 clear A1
11 clear A
14 D1 to A1
15 D to A
16 D to A
9 & -11 overflow to C bit
9 & 11 D right to A left
8 & 9 set C bit
8 & 10 D1 to A1
10 & 11 D left to A right
10 & 12 D1 to C
11 & 13 D to A right
11 & 14 D to A left

These actions are obtained from the DDP-516 Instruction Manual Vol. 2. but, as will be seen later, the same effects may be arrived at by a variety of bit patterns, not all of them accountable for from the manual. Likewise there are some inconsistencies in the description of the signals which makes it difficult to follow the action of some instructions, For example ACA ('141216) has bits 7, 9, 13, 14, 15 set to one. The manual does not mention bits 7 and 14 in its description of the signals involved, and indeed the instruction still works if they are set to zero. The CRA instruction ('140040) uses bit 11 to clear A and the manual mentions this, however bit 15 is just as effective (i.e. '140002 clears A).

A more complete description.

5.2 The Instruction Scan

A small program was written to see if any unusual bit patterns gave rise to useful instruction codes, Each of the 1024 instructions from '140000 to '141777 was applied to 15 bit patterns with the C bit both set and reset and any changes made were printed out via the on-line line printer, To ease the burden of examination of data, four symbols, 0,1,+,- were used to print out the binary, which was grouped in 4-bit bytes. A bit which remained unchanged was printed as 0 or 1, but a 0 to 1 transition was printed "+" and a 1 to 0 transition was printed "-". The CMA instruc- tion produced nothing but + and - symbols except in the C-bit, for example.

The first surprising result to emerge was the fact that bit 7 takes no part in the microcoding, although many DAP instructions use it. This anomaly was carefully and exhaustively checked by a program which cycled through all possible generic Group A instructions on all possible bit patterns in A and C.

The next result was the wealth of instructions which had the same effect. There are 32 SCB, 40 CMA and 46 RCB instructions (or twice those numbers if bit 7 is included). There is however only one for each of ICL and ICA.

5.3 Some Useful Microcoding

The potentially most useful instructions came from the set containing (8 & 15), i.e. the 1.5 cycle instructions. They will be given mnemonics as they are mentioned.

(a) Load A register with 1, LD1 - with codes '140402, '140406, '140502 and '140506. This is a combination of CRA, of which '140002 is a variant, and the extra half cycle, which adds one.
(b) add two to A register - A2A - with codes '140442, '140446, These are variations on '140042 and 6 which perform AOA, without setting the overflow bit. The extra cycle causes the sequence to occur twice.
(c) Load A with the inverse of the C-bit - CM1 with codes '140012, '140016, '140112, '140116. Since an acceptable variant of ACA is '140212 it is evident that the missing bit 9 causes the adder to be set to -1 rather than A before the C bit is added in.
(d) Add twice C to A - A2C - with codes '140452, '140456. The codes '140052 and '140056 perform ACA without setting C to overflow, it appears that the operation is being done twice.
(e) Load A with 2C-1 - ISG (for inverse sign) - with codes '140412, '140416, '140512, '140516. This is an extra cycle version of CM1. It is one of the most useful, having a direct relevance to the "sign" function calculation, described in section 5.5.
(f) copy the sign bit of A into C - CPY - this is different from CSA since the sign bit is unaffected. There are many codes for this function, the one with fewest bits set is '140321.
(g) add one to A without setting overflow - AD1 - has a code of '140212 and 3 others.
(h) add C to A without setting overflow - ADC - has a code of '140052 and 7 others, 6 of them 1.5 cycle instructions, e.g. '140453. ('140053, incidentally is one of the few "do nothing" instructions, of which there are only 40 out of 512).
It is possible to combine the action of some instructions, the following combinations may have some applications. The code given is the one with fewest bits set to 1.

 

(a) RCB/SSP '140300 reset C bit, set sign of A positive.
(b) CMA/ACA '140413 complement A then add C to A. This forms a one's complement or a two's complement according to the setting of C (1.5 cycle instruction).
(c) SCB/A2A '140602 set the C-bit, then add 2 to A. (1.5 cycle instruction),
(d) SCB/AOA '140603 set C bit, add I to A. (1.5 cycle)
(e) A2C/SCB '140612 add C twice, then set the C-bit.
(f) ACA/SCB '140613 add C , then set C-bit.

5.4 Character handling microcodes

Nearly every conceivable character handling instruction is available, including a logical inclusive "or" function between the two 8-bit characters. The mnemonics used L for left, R for right, B for the logical "or" of left and right, T for "to", and C for "clearing".

(a) RTL copy right on to left '140250
(b) LTR copy left on to right '140144
(c) BTL "or" right on to left '140241
(d) BTR "or" left on to right '140141
(e) BTB "or" to both left and right '140341
(f) BCL "or" to right, clearing left '140150
(g) BCR "or" to left, clearing right '140244
(h) ICS interchange, clear left and replace the original sign bit '140540.

Some of these, and the regular character handling codes may be combined with setting the C-bit.

(a) ICR/SCB '140640
(b) RTL/SCB '140650
(c) BTB/SCB '140741

Some instructions also perform an "or" function between the sign bit and the C-bit leaving the result in the C-bit. Denoting this function as ORC the following combinations have been noted.

(a) CMA/ORC in that order '140121
(b) CHS/ORC in that order '140124

The ORC instruction does not exist on its own.

Many other combinations exist, but it is unlikely that they will be useful. Most of them simply do too much in one go, As an example of this, consider '140570. Though only a single cycle instruction, it "or's" the left half to the right, clears the left half, restores the original sign bit and "or's" it on to the C-bit. Finally the instruction '140750 is so bizarre in its operation that it is left as an exercise for the reader.

5.5 The Algol "sign" function

The sign function is quite difficult to implement on a computer if there is not a specific instruction to perform it. It is defined as +1 if the argument is positive, 0 if it is zero and -1 if it is negative. The sequence CPY, SZE, ISG will produce the negative of the sign function by the following technique.

CPY '140321 copy the sign bit into the C-bit but leave the sign as it was (this caters for the case of '100000, which the CSA instruction would set to zero).
SZE '100040 this avoids the following instruction which will load I or -1 when the argument is already zero.
ISG '140412 this loads +1 into the A register if C is set, and -1 if C is not set.

The sequence produces the "neg sign" function, if followed by a TCA the true "sign" function may be obtained. The TCA must not be applied first, since the case of '100000 would be wrongly dealt with. Programming the same function in DAP would require six instructions and one constant location, thus

     SNZ
     JMP  *+5
     CSA
     LDA  =1
     SRC
     TCA

6. Comments on the hardware

6.1 The Skip Instructions

The SZE and SNZ instructions are the ones which prevent effective microcoding of the skips. The reason for this is that all of the other conditions being tested are independent of one another, A1 zero, A16 zero, C zero etc., but if the A register is zero then it must be both even and non negative, However, had the instruction '100040 been equivalent to a skip if non zero, then it would have been possible to skip on a strictly positive number or on one less than or equal to zero. This would have been of material assistance in the architecture of the PL-516 (and presumably FORTRAN) compilers. It is interesting to note that this fault does not occur on the H112 12-bit Honeywell computer, where the logic has been done "right way round".

6.2 The Group B Generic Instructions

These cater for such a wide variety of functions that it is difficult to see what other way they could be organized. The chief criticism is the lack of operations affecting the B-register. Operations such as copy A to B, copy B to A and logically "or" B to A would have been preferable to the IAB instruction and could have been provided within the existing logical framework.

6.3 The Group A Generic Instructions

The logic of the Group A instructions is, in part, quite difficult to follow. In particular the different usage of logical combinations of the function bits at the different cycle times. It is strange that potentially useful functions such as load 1, add 2, etc should not be mentioned in the manual, and a little frustrating that functions such as load -1, complement C-bit, copy inverse sign,, etc. should be excluded. The use of bit 7 could have led to simplifications in the logic.

Finally the shift instructions are excellent and represent the fullest range of shift types offered as standard on this size of small computer.

7. SUMMARY OF GENERIC INSTRUCTIONS, GROUP "A"

      * CMA - COMPLEMENT A
      ********************
      140001  140003  140005  140007  140011  140013  140015  140017
      140021  140022  140023  140025  140026  140027  140031  140032
      140033  140035  140036  140037  140101  140103  140105  140107
      140111  140113  140115  140117  140401  140405  140411  140415
      140421  140425  140431  140435  140501  140505  140511  140515

      * CRA - CLEAR A
      ***************
      140002  140006  140040  140060  140102  140106  140440  140460

      * SSM - SET SIGN MINUS
      **********************
      140004  140014  140104  140114  140404  140414  140500  140504
      140510  140514

      * CHS - CHANGE SIGN
      *******************
      140024  140034  140424  140434

      * CAR - CLEAR A, RIGHT
      **********************
      140044  140064  140444  140464

      * CAL - CLEAR A, LEFT
      *********************
      140050  140070  140450  140470

      * SSP - SET SIGN PLUS
      *********************
      140100  140110

      * ICL - INTERCHANGE AND CLEAR LEFT
      **********************************
      140140

      * ICR - INTERCHANGE AND CLEAR RIGHT
      ***********************************
      140240  140260

      * RCB - RESET THE C BIT
      ***********************
      140200  140201  140203  140204  140205  140207  140210  140211
      140213  140214  140215  140217  140220  140221  140222  140223
      140224  140225  140226  140227  140230  140231  140232  140233
      140234  140235  140236  140237  140301  140303  140304  140305
      140307  140311  140313  140314  140315  140317

      * CSA - COPY SIGN AND SET PLUS
      ******************************
      140320  140330

      * TCA - TWOS COMPLEMENT A
      *************************
      140403  140407  140422  140423  140426  140427  140503  140507

      * ICA - INTERCHANGE A
      *********************
      140340

      * SCB - SET THE C BIT
      *********************
      140600  140601  140604  140605  140610  140611  140614  140615
      140620  140621  140624  140625  140630  140631  140634  140635
      140700  140701  140704  140705  140710  140711  140714  140715
      140720  140721  140724  140725  140730  140731  140734  140735

      * AOA - ADD ONE TO A
      ********************
      140202  140206  140302  140306

      * AD1 - ADD ONE WITHOUT SETTING OVERFLOW
      ****************************************
      140042  140046  140443  140447  140462  140463  140466  140467

      * ACA - ADD C TO A
      ******************
      140212  140216  140312  140316

      * ADC - ADD C WITHOUT SETTING OVERFLOW
      **************************************
      140052  140056  140453  140457  140472  140473  140476  140477

      * CM1 - LOAD C - 1
      ******************
      140012  140016  140112  140116

      * LTR - COPY LEFT TO RIGHT
      **************************
      140144  140544

      * BTR - "OR" LEFT TO RIGHT
      **************************
      140141  140143  140145  140147  140151  140153  140154  140155
      140157  140541  140545  140551  140554  140555

      * BTL - "OR" RIGHT TO LEFT
      **************************
      140241  140243  140245  140247  140251  140253  140254  140255
      140257  140261  140262  140263  140265  140266  140267  140271
      140272  140273  140274  140275  140276  140277

      * RTL - COPY RIGHT TO LEFT
      **************************
      140250  140270

      * RCB/SSP
      *********
      140300  140310

      * CPY - COPY SIGN
      *****************
      140321  140322  140323  140324  140325  140326  140327  140331
      140332  140333  140334  140335  140336  140337

      * BTB - "OR" TO BOTH HALVES
      ***************************
      140341  140343  140345  140347  140351  140353  140354  140355
      140357

      * BCL - "OR" TO RIGHT., CLEARING LEFT
      *************************************
      140150

      * BCR - "OR" TO LEFT., CLEARING RIGHT
      *************************************
      140244  140264

      * LD1 - LOAD ONE INTO A REGISTER
      ********************************
      140402  140406  140502  140506

      * ISG - LOAD 2*C - 1 INTO A REGISTER
      ************************************
      140412  140416  140512  140516

      * CMA/ACA (Correction)
      *********
      140413  140417  140432  140433  140436  140437  140513  140517
      140532  140533  140536  140537

      * A2A - ADD TWO TO A
      ********************
      140442  140446

      * A2C - ADD 2*C TO A
      ********************
      140452  140456

      * ICS - INTERCHANGE, CLEAR LEFT., KEEP SIGN BIT
      ***********************************************
      140540

      * SCB/A2A
      *********
      140602  140606  140702  140706

      * SCB/AOA
      *********
      140603  140607  140622  140623  140626  140627  140703  140707
      140722  140723  149726  140727

      * A2C/SCB
      *********
      143612  140616  140712  140716

      * ACA/SCB
      *********
      140613  140617  140632  140633  140636  140637  140713  140717
      140732  140733  140736  140737

      * ICR/SCB
      *********
      140640  140660

      * RTL/SCB
      *********
      140650  140670

      * BTB/SCB
      *********
      140741  140745  140751  140754  140755  140761  140765  140771
      140774  140775

      * NOA - NO ACTION
      *****************
      140000  140010  140020  140030  140041  140043  140045  140047
      140051  140053  140054  140055  140057  140061  140062  140063
      140065  140066  140067  140071  140072  140073  140074  140075
      140076  140077  140400  140410  140420  140430  140441  140445
      140451  140454  140455  140461  140465  140471  140474  140475